* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage int.

which requires large memory density and high bandwidth. It is organized as 4banks of 8,388,608 x 8 I/O. Synchronous DRAM.

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series Document Title 256Mbi.

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